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Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MC100ES6254/D Rev. 3, 05/2004
2.5/3.3V Differential LVPECL 2x2 Clock Switch and Fanout Buffer
The Motorola MC100ES6254 is a bipolar monolithic differential 2x2 clock switch and fanout buffer. Designed for most demanding clock distribution systems, the MC100ES6254 supports various applications that require to drive precisely aligned clock signals. The device is capable of driving and switching differential LVPECL signals. Using SiGe technology and a fully differential architecture, the device offers superior digital signal characteristics and very low clock skew error. Target applications for this clock driver are high performance clock/data switching, clock distribution or data loopback in computing, networking and telecommunication systems. Features: * Fully differential architecture from input to all outputs * SiGe technology supports near-zero output skew * * * * Supports DC to 3GHz operation1 of clock or data signals LVPECL compatible differential clock inputs and outputs LVCMOS compatible control inputs Single 3.3 V or 2.5 V supply
MC100ES6254
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2.5/3.3 V DIFFERENTIAL LVPECL 2x2 CLOCK SWITCH AND FANOUT BUFFER
* 50 ps maximum device skew1 * Synchronous output enable eliminating output runt pulse generation and metastability * Standard 32 lead LQFP package * Industrial temperature range
FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A
Functional Description MC100ES6254 is designed for very skew critical differential clock distribution systems and supports clock frequencies from DC up to 3.0 GHz. Typical applications for the MC100ES6254 are primary clock distribution, switching and loopback systems of high-performance computer, networking and telecommunication systems, as well as on-board clocking of OC-3, OC-12 and OC-48 speed communication systems. Primary purpose of the MC100ES6254 is high-speed clock switching applications. In addition, the MC100ES6254 can be configured as single 1:6 or dual 1:3 LVPECL fanout buffer for clock signals, or as loopback device in highspeed data applications. The MC100ES6254 can be operated from a 3.3 V or 2.5 V positive supply without the requirement of a negative supply line.
1
The device is functional up to 3 GHz and characterized up to 2.7 GHz.
REV 3
(c) Motorola, Inc. 2004
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MC100ES6254/D
VCC Bank A CLK0 CLK0 0 1 QA0 QA0 QA1 QA1 QA2 QA2
VCC CLK1 CLK1
Bank B 0 1
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SEL0 SEL1
QB0 QB0 QB1 QB1 QB2 QB2
OEA OEB
Sync
Figure 1. MC100ES6254 Logic Diagram
CLK0
CLK0
SEL0
GND
GND 18
VCC
24
23
22
21
20
19
17 16 15 14 13 QB2 QB2 VCC QB1 QB1 VCC QB0 QB0
QA2
QA2 VCC QA1 QA1 VCC QA0 QA0
25 26 27 28
MC100ES6254
29 30 31 32 1 2 3 4 5 6 7 8 12 11 10 9
OEB
GND
SEL1
CLK1
Figure 2. 32-Lead Package Pinout (Top View)
2
CLK1
GND
VCC
VCC
VCC
OEA
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Table 1. PIN CONFIGURATION
Pin CLK0, CLK0 CLK1, CLK1
OEA, OEB
I/O Input Input Input Input Output Supply Supply
Type LVPECL LVPECL LVCMOS LVCMOS LVPECL GND VCC Differential reference clock signal input 0 Differential reference clock signal input 1 Output enable Clock switch select Differential clock outputs (banks A and B) Negative power supply
Function
SEL0, SEL1 QA[0-2], QA[0-2] QB[0-2], QB[0-2] GND VCC
Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation
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Table 2. FUNCTION TABLE
Control
OEA
Default 0
0
1
QA[0-2], Qx[0-2] are active. Deassertion of OE can be QA[0-2] = L, QA[0-2] = H (outputs disabled). Assertion asynchronous to the reference clock without generation of OE can be asynchronous to the reference clock of output runt pulses without generation of output runt pulses QA[0-2], Qx[0-2] are active. Deassertion of OE can be QA[0-2] = L, QA[0-2] = H (outputs disabled). Assertion asynchronous to the reference clock without generation of OE can be asynchronous to the reference clock of output runt pulses without generation of output runt pulses Refer to Table 3
OEB
0
SEL0, SEL1
00
Table 3. CLOCK SELECT CONTROL
SEL0 0 0 1 1 SEL1 0 1 0 1 CLK0 routed to QA[0:2] and QB[0:2] --QA[0:2] QB[0:2] CLK1 routed to --QA[0:2] and QB[0:2] QB[0:2] QA[0:2] Application Mode 1:6 fanout of CLK0 1:6 fanout of CLK1 Dual 1:3 buffer Dual 1:3 buffer (crossed)
Table 4. ABSOLUTE MAXIMUM RATINGSa
Symbol VCC VIN VOUT IIN IOUT TS a. Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC+0.3 VCC+0.3 20 50 125 Unit V V V mA mA C Condition
Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
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Table 5. GENERAL SPECIFICATIONS
Symbol VTT MM HBM CDM LU CIN JA Thermal resistance junction to ambient JESD 51-3, single layer test board Characteristics Output termination voltage ESD Protection (Machine model) ESD Protection (Human body model) ESD Protection (Charged device model) Latch-up immunity 200 2000 1500 200 4.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3 110 TA=-40 TJ=+110 Min Typ VCC - 2a Max Unit V V V V mA pF C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C C Inputs Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min MIL-SPEC 883E Method 1012.1 Condition
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JESD 51-6, 2S2P multilayer test board
JC
Thermal resistance junction to case Operating junction temperatureb (continuous operation) MTBF = 9.1 years
TFunc a. b.
Functional temperature range
Output termination voltage VTT=0 V for VCC=2.5 V operation is supported but the power consumption of the device will increase. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (See application note AN1545 and the application section in this data sheet for more information). The device AC and DC parameters are specified up to 110C junction temperature allowing the MC100ES6254 to be used in applications requiring industrial temperature range. It is recommended that users of the MC100ES6254 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application.
Table 6. DC CHARACTERISTICS (VCC = 3.3 V 5% or 2.5 V 5%, TJ = 0 to +110C)
Symbol Characteristics Min Typ Max Unit Condition LVCMOS control inputs (OEA, OEB, SEL0, SEL1) VIL VIH IIN VPP VCMR VOH VOL Input voltage low Input voltage high Input Currenta 2.0 100 0.8 V V A VIN=VCC or VIN=GND Differential operation Differential operation IOH = -30 mAd IOL = -5 mAe
LVPECL clock inputs (CLK0, CLK0, CLK1, CLK1) AC differential input voltageb Differential cross point voltagec 0.1 1.0 1.3 VCC-0.3 VCC-1.005 VCC-1.705 VCC-1.705 52 VCC-0.7 VCC-1.5 VCC-1.3 85 V V
LVPECL clock outputs (QA0-2, QA0-2, QB0-2, QB0-2) Output High Voltage Output Low Voltage VCC=3.3 V 5% VCC=2.5 V 5% VCC-1.2 VCC-1.9 VCC-1.9 V V
IGND a. b. c. d. e.
Maximum Quiescent Supply Current without output termination current
mA
GND pin
Input have internal pullup/pulldown resistors that affect the input current. VPP is the minimum differential input voltage swing required to maintain AC characteristic. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. Equivalent to a termination 50 to VTT. ICC calculation: ICC = (number of differential output pairs used) * (IOH + IOL) + IGND ICC = (number of differential output pairs used) * (VOH-VTT)/Rload +(VOL-VTT)/Rload) + IGND
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Table 7. AC CHARACTERISTICS (VCC = 3.3 V 5% or 2.5 V 5%, TJ = 0 to +110C)a
Symbol VPP VCMR VO(P-P) Characteristics Differential input voltageb (peak-to-peak) Differential input crosspoint voltagec Differential output voltage (peak-to-peak) fO < 1.1 GHz fO < 2.5 GHz fO < 3.0 GHz Input Frequency Propagation delay CLK, 1 to QA[] or QB[] Output-to-output skew Output-to-output skew(part-to-part) Output pulse skewe Output duty cycle Output cycle-to-cycle jitter Output Rise/Fall Time Output disable time Output enable time tREF < 100 MHz tREF < 800 MHz RMS (1 ) 0.05 2.5T + tPD 3T + tPD 49.4 45.2 Min 0.3 1.2 0.45 0.35 0.20 0 360 485 0.7 0.55 0.35 3000d 610 50 250 60 50.6 54.8 1 300 3.5T + tPD 4T + tPD Typ Max 1.3 VCC-0.3 Unit V V V V V MHz ps ps ps ps % % ps ps ns ns DCfref = 50% DCfref = 50% SEL0 SEL1 20% to 80% T = CLK period T = CLK period Differential Differential Differential Condition
fCLK tPD tsk(O) tsk(PP)
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tSK(P) DCO tJIT(CC) tr , tf tPDLf tPLDg a. b. c.
AC characteristics apply for parallel output termination of 50 to VTT. VPP is the minimum differential input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. The MC100ES6254 is fully operational up to 3.0 GHz and is characterized up to 2.7 GHz. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |. Propagation delay OE deassertion to differential output disabled (differential low: true output low, complementary output high). Propagation delay OE assertion to output enabled (active). CLKX CLKX
d. e. f. g.
50% OEX tPDL (OEX to Qx[]) tPLD (OEX to Qx[]) Outputs disabled
Qx[] Qx[]
Figure 3. MC100ES6254 output disable/enable timing
Differential Pulse Generator Z = 50
ZO = 50
ZO = 50
RT = 50 VTT
DUT MC100ES62
RT = 50 VTT
Figure 4. MC100ES6254 AC test reference
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APPLICATIONS INFORMATION
Example Configurations
2x2 clock switch CLK0 CLK1 SEL0 SEL1 MC100ES6254 SEL0 SEL1 Switch configuration CLK0 clocks system A and system B CLK1 clocks system A and system B CLK0 clocks system A and CLK1 clocks system B CLK1 clocks system B and CLK1 clocks system A System A 3
3
System B
Understanding the junction temperature range of the MC100ES6254 To make the optimum use of high clock frequency and low skew capabilities of the MC100ES6254, the MC100ES6254 is specified, characterized and tested for the junction temperature range of TJ=0C to +110C. Because the exact thermal performance depends on the PCB type, design, thermal management and natural or forced air convection, the junction temperature provides an exact way to correlate the application specific conditions to the published performance data of this data sheet. The correlation of the junction temperature range to the application ambient temperature range and vice versa can be done by calculation: TJ = TA + Rthja Ptot Assuming a thermal resistance (junction to ambient) of 54.4C/W (2s2p board, 200 ft/min airflow, refer to table 4) and a typical power consumption of 467 mW (all outputs terminated 50 to VTT, VCC=3.3 V, frequency independent), the junction temperature of the MC100ES6254 is approximately TA + 24.5C, and the minimum ambient temperature in this example case calculates to -24.5C (the maximum ambient temperature is 85.5C. Refer to Table 8). Exceeding the minimum junction temperature specification of the MC100ES6254 does not have a significant impact on the device functionality. However, the continuous use the MC100ES6254 at high ambient temperatures requires thermal management to not exceed the specified maximum junction temperature. Refer to the Application Note AN1545 for a power consumption calculation guideline. Table 8. Ambient temperature ranges (Ptot = 467 mW)
Rthja (2s2p board) TA, mina -28C -25C -24.5C -23.5C -22C TA, max 82C 85C 85.5C 86.5C 88C
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0 0 1 1
0 1 0 1
1:6 Clock Fanout Buffer CLK0 CLK1
0 0
SEL0 SEL1 MC100ES6254
Loopback device System-Tx CLK0 SEL0 SEL1 System-Rx QB[] CLK1 Receiver QA[] Transmitter
Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min
59.0C/W 54.4C/W 52.5C/W 50.4C/W 47.8C/W
MC100ES6254
a.
The MC100ES6254 device function is guaranteed from TA=-40C to TJ=110C
SEL0 0 0 1 1
SEL1 0 1 0 1
Switch configuration System loopback Line loopback Transmit / Receive operation System and line loopback
Maintaining Lowest Device Skew The MC100ES6254 guarantees low output-to-output bank skew of 50 ps and a part-to-part skew of maximum 250 ps. To ensure low skew clock signals in the application, both outputs of any differential output pair need to be terminated identically, even if only one output is used. When fewer than all nine output pairs are used, identical termination of all output pairs within the output bank is recommended. If an entire output bank is not used, it is recommended to leave all of these outputs open and unterminated. This will reduce the device power consumption while maintaining minimum output skew.
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Power Supply Bypassing The MC100ES6254 is a mixed analog/digital product. The differential architecture of the MC100ES6254 supports low noise signal operation at high frequencies. In order to maintain its superior signal quality, all VCC pins should be bypassed by high-frequency ceramic capacitors connected to GND. If the spectral frequencies of the internally generated switching noise on the supply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth.
VCC 33...100 nF 0.1 nF
VCC MC100ES6254
Figure 5. VCC Power Supply Bypass
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OUTLINE DIMENSIONS
4X
6 D1
PIN 1 INDEX
0.20 H
A-B D e/2 3 A, B, D
D1/2
32 25
1
E1/2 A 6 E1
DETAIL G 8
B E E/2 4
F
F
17
DETAIL G
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS A, B, AND D TO BE DETERMINED AT DATUM PLANE H. 4. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE C. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08-mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION: 0.07-mm. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1-mm AND 0.25-mm FROM THE LEAD TIP.
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7
9
D D 4
D/2
4X
0.20 C
A-B D
H
28X
e
32X
0.1 C
SEATING PLANE
C
DETAIL AD
PLATING BASE METAL
b1 c c1
b
8X
5
8
(1)
R R2 R R1
0.20
M
C A-B D
SECTION F-F
A
A2
0.25
GAUGE PLANE
A1
(S) (L1)
L
DETAIL AD
DIM A A1 A2 b b1 c c1 D D1 e E E1 L L1 q q1 R1 R2 S
MILLIMETERS MIN MAX 1.40 1.60 0.05 0.15 1.35 1.45 0.30 0.45 0.30 0.40 0.09 0.20 0.09 0.16 9.00 BSC 7.00 BSC 0.80 BSC 9.00 BSC 7.00 BSC 0.50 0.70 1.00 REF 0 7 12 REF 0.08 0.20 0.08 --0.20 REF
FA SUFFIX CASE 873A-03 ISSUE PACKAGE LQFP B CASE 873A-02 ISSUE B
DATE 03/10/00
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NOTES
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NOTES
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NOTES
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